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HAT1097R, HAT1097RJ
Silicon P Channel Power MOS FET High Speed Power Switching
REJ03G0529-0100 Rev.1.00 Feb.15.2005
Features
* * * * Low on-resistance Capable of 4.5 V gate drive High density mounting "J" is for Automotive application High temperature D-S leakage guarantee Avalanche rating
Outline
RENESAS Package code: PRSP0008DD-A (Previous code: SOP-8 ) 56
78 DDDD
8
5 76
4 G 3 12 4
1, 2, 3 Source 4 Gate 5, 6, 7, 8 Drain
SSS 123
Absolute Maximum Ratings
(Ta = 25C)
Item Symbol Ratings HAT1097R HAT1097RJ Unit V V A A A mJ W
Drain to source voltage VDSS -60 -60 Gate to source voltage VGSS 20 20 Drain current ID -5 -5 Note1 Drain peak current ID (pulse) -40 -40 Avalanche current IAPNote3 -- -5 Avalanche energy EARNote3 -- 2.14 Channel dissipation PchNote2 2 2 Channel temperature Tch 150 150 Storage temperature Tstg -55 to +150 -55 to +150 Notes: 1. PW 10s, duty cycle 1% 2. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW 10 s 3. Value at Tch = 25C, Rg 50
C C
Rev.1.00, Feb.15.2005, page 1 of 7
HAT1097R, HAT1097RJ
Electrical Characteristics
Item Drain to source breakdown voltage Gate to Source breakdown voltage Zero gate voltage drain current HAT1097R Zero gate voltage drain current HAT1055RJ Gate to source leak current Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time Notes: 4. Pulse test Symbol V(BR)DSS V(BR)GSS IDSS IDSS IDSS IGSS VGS(off) |yfs| RDS(on) RDS(on) Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDF trr Min -60 20 -- -- -- -- -1.0 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- 5 60 90 1350 135 85 21 3 4 20 15 55 10 -0.85 25 Max -- -- -1 -- -10 10 -2.5 -- 76 130 -- -- -- -- -- -- -- -- -- -- -1.10 -- Unit V V A A A A V S m m pF pF pF nC nC nC ns ns ns ns V ns Test Conditions ID = -10 mA, VGS = 0 IG = 100 A, VDS = 0 VDS = -60 V, VGS = 0 VDS = -48 V, VGS = 0 Ta = 125C VGS = 16 V, VDS = 0 VDS = -10 V, ID = -1 mA ID = -2.5 ANote4, VDS = -10 V ID = -2.5 ANote4, VGS = -10 V ID = -2.5 ANote4, VGS = -4.5 V VDS = -10 V, VGS = 0 f = 1 MHz VDD = -25 V VGS = -10 V ID = -5 A VGS = -10 V, ID= -2.5 A VDD -30 V RL = 12 RG = 4.7 IF = -5 A, VGS = 0Note4 IF = -5 A, VGS = 0 diF/dt = 100 A/s
Rev.1.00, Feb.15.2005, page 2 of 7
HAT1097R, HAT1097RJ
Main Characteristics
Power vs. Temperature Derating 4.0 -100 Maximum Safe Operation Area 10 s 10 0 s PW 1 ms =1 0m DC s
Op era tio n( PW
N
Pch (W)
(A) Drain Current ID
Test Condition: When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) PW 10 s
-30 -10 -3 -1 -0.3
3.0
Channel Dissipation
2.0
-0.1 Operation in
1.0
this area is -0.03 limited by R DS(on)
< 1 ote 0s5 )
-0.01 -0.003 Ta = 25C 1 shot Pulse -0.001 -0.1 -0.3 -1 -3 -10 -30 -100 Drain to Source Voltage VDS (V) Note 5: When using the glass epoxy board (FR4 40 x 40 x 1.6 mm) Typical Output Characteristics Typical Transfer Characteristics -10 -10 V Pulse Test VDS = -10 V Pulse Test
0
50
100
150 Ta (C)
200
Ambient Temperature
-10
(A)
-3.5 V
Drain Current ID
-6
-4
-2 VGS =-2.5 V 0 -2 -4 -6 Drain to Source voltage -8 VDS (V) -10
Drain Current ID
(A)
-8
-6 V -4.5 V
-8
-6
-4
-2 Tc = 75C 0 -1 -2 25C -25C -3 -4 -5
Gate to Source Voltage
VGS (V)
Drain to Source Saturation Voltage VDS(on) (V)
-1 Pulse Test -0.8
Drain to Source on State Resistance RDS(on) ()
Drain to Source Saturation Voltage vs. Gate to Source Voltage
Static Drain to Source on State Resistance vs. Drain Current 1.0 Pulse Test 0.5 0.2 0.1 VGS = -4.5 V
-0.6
-0.4 ID = -5 A -0.2 0 0 -2 A -1 A -4 -8 -12 -16 -20
0.05
-10 V
0.02 0.01 -1
-3
-10
-30
-100
Gate to Source Voltage
VGS (V)
Drain Current ID (A)
Rev.1.00, Feb.15.2005, page 3 of 7
HAT1097R, HAT1097RJ
Static Drain to Source on State Resistance RDS(on) ()
Forward Transfer Admittance |yfs| (S)
Static Drain to Source on State Resistance vs. Temperature 0.25 Pulse Test 0.20 -5 A 0.15 VGS = -4.5 V 0.10 -5 A -1, -2 A ID = -1, -2 A
50 20 10 5 2 1
Forward Transfer Admittance vs. Drain Current
Tc = -25C 25C 75C
0.05 0 -40
-10 V 0 40 80
V DS = -10 V Pulse Test -1 -3 -10 -30 -100
120 Tc (C)
160
0.5 -0.1 -0.3
Case Temperature
Drain Current ID (A) Typical Capacitance vs. Drain Source Voltage 5000
Capacitance C (pF)
Body-Drain Diode Reverse Recovery Time 1000
Reverse Recovery Time trr (ns)
500
di / dt = 100 A / s VGS = 0, Ta = 25C
2000 1000 500 200 100 50 Coss Crss 20 10 VGS = 0 f = 1 MHz 0 -10 -20 -30 -40 (V) -50 Ciss
200 100 50
20 10 -0.1 -0.3
-1
-3
-10
-30
-100
Reverse Drain Current
IDR (A)
Drain Source Voltage VDS Switching Characteristics
Gate to Source Voltage VGS (V) Switching Time t (ns)
Dynamic Input Characteristics 0
VDS (V)
-20
VDD = -10 V -25 V -50 V ID = -5 A
0
1000 300 100 30 10 3 1 -0.1 -0.3 tf VGS = -10 V, VDS = -30 V PW = 5 s, duty < 1 % -1 -3 -10 -30 Drain Current ID (A) -100 t d(off) tr t d(on)
-4
Drain to Source Voltage
-40 VDS -60 VDD = -10 V -25 V -50 V VGS
-8
-12
-80
-16 -20 40
-100
0
8 16 24 32 Gate Charge Qg (nc)
Rev.1.00, Feb.15.2005, page 4 of 7
HAT1097R, HAT1097RJ
Reverse Drain Current vs. Source to Drain Voltage Maximum Avalanche Energy vs. Channel Temperature Derating
Repetitive Avalanche Energy EAR (mJ)
-10
2.5 I AP = -5 A V DD = -25 V duty < 0.1 % Rg > 50
(A)
Pulse Test -8 -10 V -6 -5 V V GS = 0, 5 V
Reverse Drain Current IDR
2.0
1.5
-4
1.0 0.5 0 25
-2 0 0
-0.4 -0.8 -1.2 -1.6 -2.0 Source Drain Voltage VSD (V)
50
75
100
125
150
Channel Temperature Tch (C) Avalanche Waveform EAR = 1 2 L * I AP *
2
Avalanche Test Circuit
VDSS VDSS - V DD
V DS Monitor
L I AP Monitor
V (BR)DSS I AP VDD ID V DS
Rg Vin -15 V
D. U. T
50 0 VDD
Switching Time Test Circuit Vin Monitor Rg D.U.T. RL Vout Monitor Vin
Switching Time Waveform
10% 90%
Vin -10 V
V DD = -30 V Vout td(on)
90% 10% tr td(off)
90% 10% tf
Rev.1.00, Feb.15.2005, page 5 of 7
HAT1097R, HAT1097RJ
Normalized Transient Thermal Impedance vs. Pulse Width
Normalized Transient Thermal Impedance s (t)
10
D=1 1
0.1
0.05
0.02
0.01
0.01
ch - f(t) = s (t) x ch - f ch - f = 125C/W, Ta = 25C When using the glass epoxy board (FR4 40 x 40 x 1.6 mm)
p ot uls e
PDM PW T
0.001
h 1s
D=
PW T
0.0001 10
100
1m
10 m
100 m 1 10 Pulse Width PW (S)
100
1000
10000
Rev.1.00, Feb.15.2005, page 6 of 7
HAT1097R, HAT1097RJ
Package Dimensions
JEITA Package Code P-SOP8-3.95 x 4.9-1.27 RENESAS Code PRSP0008DD-A Previous Code FP-8DA MASS[Typ.] 0.085g
*1 D
8 5
F
bp b1
*2 E
HE
Index mark 1 Z 4
Terminal cross section
c1 c
*3
bp
xM
NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
e
L1
Reference Symbol
Dimension in Millimeters Min Nom 4.90 3.95 Max 5.3
D E A2 A1 A 0.10
0.14
0.25 1.75
A1
A
bp
0.34
0.42 0.40
0.50
L
Detail F
b1 c c1 0 HE e x y Z L L1 0.40 5.80 0.19
0.22 0.20
0.25
8 6.10 1.27 0.25 0.1 0.75 0.60 1.08 1.27 6.20
y
Ordering Information
Part Name HAT1097R-EL-E HAT1097RJ-EL-E Quantity 2500 pcs. 2500 pcs. Taping Taping Shipping Container
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product.
Rev.1.00, Feb.15.2005, page 7 of 7
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .2.0

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